1. Field of the Invention
The present invention is related to a semiconductor device, particularly, to a cell base integrated circuit incorporating CMOS (complementary metal oxide semiconductor) primitive cells.
2. Description of the Related Art
Avoiding malfunction and decrease in the operating speed due to power supply noise is one of the requirements of LSI's (large scale integrated circuit) incorporating CMOS primitive cells, especially LSI's in which analogue and digital circuits are monolithically integrated. Therefore, LSI's often incorporate a decoupling capacitor for several primitive cells to thereby improve tolerance to the power supply noise.
Japanese Laid Open Patent Application No. Jp-A Heisei 2-241061 discloses a CMOS gate array incorporating bypass capacitors (decoupling capacitors) between the power supply and ground to absorb the noise. The disclosed CMOS gate array includes an array of primitive cells each comprised of a PMOS transistor(s) and an NMOS transistor(s). In this CMOS gate array, decoupling capacitors are prepared by using unused transistors within the primitive cells. Specifically, the source and drain of an unused PMOS transistor within a primitive cell is connected to a power supply line, and the gate thereof is connected to a ground line. Correspondingly, the source and drain of an unused NMOS transistor within a primitive cell is connected to a ground line, and the gate thereof is connected to a power supply line. Such connection allows the unused PMOS and NMOS transistors to function as decoupling capacitors.
FIGS. 1A and 1B illustrate an exemplary layout of primitive cells and decoupling capacitors disclosed in the above-described Patent Application. In detail, FIG. 1A illustrates layouts of a well layer, a diffusion layer, a polysilicon layer, and a contact layer, which are integrated within or on the substrate, and FIG. 1B illustrates a metal interconnection layer integrated on or over these layers.
Referring to FIG. 1A, the conventional CMOS array is composed of a circuit region, and a pair of tap regions 900 and 910, which are used to stabilize the ground level of the transistors within the inverter cells and the decoupling capacitors. The circuit region incorporates multiple inverter cells (which are a sort of CMOS primitive cells) and a decoupling capacitor cell formed of unused PMOS and NMOS transistors within the circuit region. Referring to FIG. 1B, the metal interconnection layer is composed of a power supply line 400 connected to a power supply VDD, and a ground line 500 connected to the ground GND. The power supply line 400 and the ground line 500 are extended in the X-axis direction.
Integrated within the CMOS inverter cells are PMOS transistors P10, P20, P30, NMOS transistors N10, N20, and N30. The PMOS transistors P10, P20, and P30 include P-type diffusion layers 110 integrated within an N-type well 100, and the NMOS transistors N10, N20, and N30 include N-type diffusion layers 120 integrated within an P-type well 200. The PMOS transistors P10, P20, P30, NMOS transistors N10, N20, and N30 have commonly-connected gate electrodes 300, and the drains of the PMOS transistors P10, P20, P30, and the NMOS transistors N10, N20, N30 are commonly connected through interconnections 600. The sources of the PMOS transistors P10, P20, and P30 are connected to the power supply line 400 through via contacts 130 and interconnections 410, and the sources of the NMOS transistors N10, N20, and N30 are connected to the ground line 500 through the via contacts 140 and interconnections 510.
The tap region 900 is positioned under the power supply line 400. The tap region 900 includes an N-type diffusion layer 140 which provides an electrical connection of the N-well 100, within which the PMOS transistors P10, P20, and P30 are integrated, to the power supply VDD. The electric potential of the N-well 100 is stabilized by the electrical connection between the N-well 100 and the power supply VDD.
Correspondingly, the tap region 910 is positioned under the ground line 500. The tap region 910 include a P-type diffusion layer 150 which provides an electrical connection of the P-well 200, within which the NMOS transistors N10, N20, and N30 are integrated, to the ground GND. The electric potential of the P-well 200 is stabilized by the electrical connection between the P-well 200 and the ground GND.
The decoupling capacitor cell is composed of unused PMOS and NMOS transistors within the circuit region. Specifically, as shown in FIG. 1A, the decoupling capacitor cell is composed of a PMOS transistor DC10 and an NMOS transistor DC20. The PMOS transistor DC10 has a gate electrode 310 connected to the ground line 500 through an interconnection 520, and the NMOS transistor DC20 has a gate electrode 320 connected to the power supply line 400 through an interconnection 420. The source and drain of the PMOS transistor DC10 are connected to the power supply line 400 through via contacts 130, and interconnections 420 and 430, while the source and drain of the NMOS transistor DC20 are connected to the ground line 500 through via contacts 130 and interconnections 520 and 530. In this structure, the gate capacitances of the PMOS transistor DC10 and NMOS transistor DC20 are used as the decoupling capacitors, and thereby effectively suppress the power supply noise of the power supply VDD and the ground GND.
In the above-described conventional LSI, one decoupling capacitor cell is prepared for multiple primitive cells. The decoupling capacitors within the decoupling capacitor cell are formed of gate capacitances of unused transistors within the circuit region. Such device structure requires increased total gate areas for effectively suppressing the power supply noise. Therefore, the conventional LSI suffers from a problem that an increased number of decoupling capacitor cells are required to suppress the power supply noise to a desired degree, and therefore the chip size is undesirably increased.